A nonvolatile memory is a type of memory that retains stored data when power is removed. There are various types of nonvolatile memories, including read only memories (ROMs), programmable read only memories (PROMs), erasable programmable read only memories (EPROMs), and electrically erasable programmable read only memories EEPROMs). An EEPROM is erased using ultraviolet light and an EEPROM is erased using an electrical signal. An electrical signal is used to write EPROMS and EEPROMS. In a conventional flash EEPROM ("flash" indicating all memory cells or sectors of cells can be erased at once), memory cells are simultaneously erased to a low threshold voltage and then programmed, either individually or in small groups, to a high threshold voltage. EPROMs and EEPROMs are commonly used in data processing systems that require a nonvolatile memory that is reprogrammable. For convenience, EEPROMs and EPROMs are referred to collectively herein as EPROMS.
A typical device structure for EPROMS is the floating-gate polysilicon transistor. A typical floating gate structure is illustrated in FIG. 1. As depicted in FIG. 1, a floating gate 10, sandwiched between two insulator layers 20 and 60, is between the substrate 30 and the ordinary select-gate electrode 40. The structure depicted in FIG. 1 is a stacked gate memory cell, the word stacked indicating that the floating gate 10 is stacked over the source 50 and drain 70 portions of the substrate. Another EPROM structure is a split gate structure wherein the portion of the floating gate only overlies the drain and no portion of the floating gate overlies the source. Split gate EPROM device structures are described in U.S. Pat. No. 5,349,220, to Hong which is hereby incorporated by reference. As a result, in EPROMS, the select-gate voltage must be capacitively coupled in series with the floating gate rather than directly to the underlying channel.
There are n-channel and p-channel devices with the above structures. In the n-channel devices, the source and drain are doped with an n-type dopant and the substrate is doped with a p-type dopant. In p-channel devices, the source and drain contain p-type dopant and the substrate contains n-type dopant. In silicon based substrates, such as silicon or silicon-germanium (SiGe) alloys, an example of a p-type dopant is boron and example of suitable n-type dopants are arsenic and phosphorous.
EPROMS are programmed by applying a set of bias voltages to the device depicted in FIG. 1. The voltage applied to the select-gate (hereinafter referred to as a control gate) is V.sub.C, the voltage applied to the drain is V.sub.D, and the voltage applied to the source is V.sub.S. Voltage differences, typically referred to as biases, between these various terminals are designated in the following manner: e.g., V.sub.CS =V.sub.C -V.sub.S etc. In n-channel devices writing biases are used to introduce additional negative charge onto the floating gate, thereby writing the cell. However, if the charged state is chosen as the "unwritten" state, introducing additional negative charge onto the floating gate will erase the cell. Bias conditions that are used to introduce a more negatively charged state are different from bias conditions that are used to read the charged state or to create a more positively charged state.
These write biases are typically a high control gate-to-source voltage (V.sub.CS) and/or a high drain-to-source voltage (V.sub.DS). These programming voltages are sufficient to cause a transfer of electrons from the bulk of the device (channel 80 and/or source 50 and/or drain 70) region to the floating gate 10 where they are trapped, thereby charging the floating gate more negatively. Charge is trapped in the floating gate 10 because the floating gate is isolated from the select-gate 40 by an insulating oxide layer 60 and from the drain-source-substrate region by another thin oxide insulating layer 20. The effect of trapping electrons on the floating gate is to raise the threshold voltage (V.sub.T) to some predetermined level. Furthermore, these programming voltages are outside of the range of normal reading bias conditions so that an inadvertent write does not occur during reading.
EPROMS typically include an array of floating-gate transistors. The V.sub.T of a given cell can be determined by a sense amplifier when read and decoded into its logic value. For example, in a conventional two-state memory, a high V.sub.T which has been achieved by writing as described above is decoded as a logic one, and the intrinsic V.sub.T (the V.sub.T of a device which has not been written by adding negative charge to the floating gate 10) is decoded as a logic zero. Because the floating gate is isolated, the cell can remain programmed or erased for periods of up to 10 years and even longer.
One method that is employed to introduce negative charge into the floating gate is channel hot electron injection (CHEI). The objective of CHEI is to heat electrons in the channel to high enough energies so that they enter the conduction band of the oxide layer 20, pass through it, and enter the floating gate 10. In CHEI the electron current which charges the floating gate I.sub.F) is initiated by the electron current flowing from the source to the drain (I.sub.DS). If I.sub.DS goes to zero, then I.sub.F goes to zero and, as a result, more negative charge is not introduced into the floating gate.
In order to generate a large enough charge by CHEI to charge the floating gate in a reasonable amount of time, the electrons must be heated in the device to overcome the conduction band energy barrier between the semiconductor and the oxide. In the case of the silicon/SiO.sub.2 interface, this barrier is about 3.2 eV. These "hot-electrons" are termed "hot" because their distribution in terms of energy contains a greater proportion of high energy carriers than are present in thermal equilibrium in the crystal lattice of the silicon substrate. The "hot electrons" gain their energy from electric fields and potential energy drops in the device.
In CHEI some fraction of the electrons which travel from the source 50 to the drain 70 (these electrons are part of the drain-source current, designated as I.sub.DS) gain enough energy from the source-drain potential drop to have 3.2 eV at the oxide interface. Some fraction of the channel hot electrons that have this energy enter the conduction band of the oxide layer 20 and are conveyed to the floating gate 10.
An electron, moving from the source to the drain, gains an amount of energy that is essentially limited to the high field potential drop in the channel. The high field potential drop in the channel is typically less than the sum of the source-drain bias (V.sub.DS) and the built-in potential between the channel and the drain. Typically the built-in potential of the channel to the drain does not exceed 0.3 V. The sum of these values is referred to as E.sub.max.
In the absence of effects such as electron-electron scattering, conservation of energy dictates that the electrons which fall through the potential drop E.sub.max can gain an amount of energy that is, at most, equal to the potential energy drop which is the product of E.sub.max and the electronic charge (q; where q is the charge of the electrons in coulombs). (By way of background, an electric potential is expressed in units of V. If an electron falls through a potential drop of V, it gains energy (q.times.V) which is expressed in units of eV.) The effects of electron-electron scattering are typically insignificant because the energy required for electron injection into the floating gate is 3.2 eV, and very few electrons obtain this energy threshold through such effects.
A V.sub.DS of 3.2 V does not currently provide for negatively charging the floating gate (referred to herein as the "write") in a practical amount of time. A practical amount of time is currently about 1 ms or less. In current devices, at least 5 V must be introduced into the device in order for the high field potential energy drop in the channel to be the requisite 3.2 eV or higher. Even higher voltages are required if smaller write times are desired.